FIG. 7 shows circuit diagram of a conventional PLL circuit. In FIG. 7, synchronization separation circuit 1 takes synchronous signal away from a signal inputted from the outside. In a period when one of the input is L, phase comparator 2 changes an output voltage in accordance with a proportion high/low of the other input. Low-pass filter 3 removes noise signal from an output signal of phase comparator 2 and outputs it. Amplifier 4 amplifies a signal outputted from low-pass filter 3. Voltage control oscillator 5 changes an output frequency based on the voltage of a signal outputted from amplifier 4. Frequency divider 6 divides an output signal of voltage control oscillator 5 into 1/n.
Next, operation of the above-configured conventional PLL circuit is described.
FIG. 8 is a timing chart showing the operating state of a conventional PLL circuit. The top portion of FIG. 8 shows the voltage waveform of signal a, which is outputted from synchronization separation circuit 1 and inputted to phase comparator 2. The middle portion shows the voltage waveform of signal b, which is outputted from frequency divider 6 and inputted to phase comparator 2. Shown at the bottom is the voltage waveform of signal c, which is outputted from phase comparator 2 and inputted to low-pass filter 3.
As shown in FIG. 8, synchronization separation circuit 1 outputs to phase comparator 2 a signal which stays in low state (described “L”) for a certain time period. When the signal a from synchronization separation circuit 1 is low, phase comparator 2 lowers its output voltage during a period while the other signal b is high (“H”). Contrary, when the other input signal b is low, phase comparator 2 raises its output voltage during the duration.
Signal C which was influenced in the level by signal a from synchronization separation circuit 1 and the other signal b proceeds via low-pass filter 3 and amplifier 4 to operate voltage control oscillator 5. The signal inputted to voltage control oscillator 5 turns out to be an output signal which oscillates at n-times the frequency. Frequency divider 6 divides the inputted signal into 1/n.
By connecting an AD converter (not shown) at the end stage of synchronization separation circuit 1 and inputting an analog signal to phase comparator 2, a phase synchronous control can be carried out by making used of a rectangular wave signal in place of analog signal. Patent Document 1 is an example of prior art technical documents related to the present invention.
However, if a digital signal is inputted to phase comparator 2 of a PLL circuit of conventional structure, period of signal input with one of the signals inputted to phase comparator 2 is shortened corresponding to an interval of sampling the digital signal. Consequently, the output of signal c which has undergone the level-shifting becomes smaller. This leads to instability of the fluctuation amount with the output frequency. This makes it difficult to adjust the phase accurately.
[Patent Document 1]                Japanese Patent Unexamined Publication No. S62-131630        